GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

In this paper, the CMOS gate matrix layout problem is formulated and solved as a n artificial intelligence planning problem in which a “plan” (the solution algorithm) is to be generated to achieve a “goal” (the gate matrix layout). The overall goal consists of many subgoals, each of which corresponds to the placement of a gate to a slot, and to the routing of associated nets connecting to that gate. As different nets compete for track (resource) usage, these subgoals interact (interfere) with each other, rendering suboptimal solutions. In this paper, such interaction among subgoals is managed with two artificial intelligence planning techniques: hierarchical subgoal organization and domain independent search control policies. The subgoal hierarchy facilitates an objective classification of the subgoals into priority classes according to a proposed distance measure of connectivity. Two search control policies (general problem solving heuristics)-most-constraint (MC) and least impact (L1)-are used to guide the search process. The MC policy states that the subgoal whose solution has most constraints should be attempted first. The LI policy states that among many alternate solutions, the one that consumes the least amount of resources, and hence, preserves the most flexibility should be chosen. Using these techniques, we developed a planning-based gate matrix layout algorithm, called GM-Plan, which combines the gate placement and net routing into a single, incremental problem solving loop. Encouraging results have been observed in a number of test examples.